Abstract
The discrete wavelet transform (DWT) has received considerable attention in the context of image processing due to its temporal and frequency characteristics. A specific VLSI architecture for the forward/inverse DWT is presented. The characteristics of the structure and coefficients are utilized to reduce the circuit area. In addition, the Booth algorithm and balanced pipelines have been adopted which result in a high throughput at 2 outputs per clock and 5 clocks' pipeline latency. This design described and verified by the VHDL is synthesized by the Synopsys synthesizer. The synthesis results show that the gate-level circuit contains 5058 gates and the throughput can reach 110 M points/s when LSI 10 K CMOS technology is used.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
