A VLSI architecture design of CAVLC decoder

Abstract

Variable length code is an integral component of many international standards on image and video compression. Recently, context-based adaptive variable length coding (CAVLC) is adopted by the emerging JVT (also called H.264 in ITU, and AVC in MPEG-4). In this paper, we describe a novel architecture for CAVLC decoder, including a coeff_token decoder, level decoder, total_zeros decoder and run_before decoder. Together with a barrel shifter and controller, the pipeline architecture can decode every syntax element in one clock cycle. Therefore, it is very suitable for video applications that require high throughput.