Abstract
Multiple-input multiple-output (MIMO) systems are of significant interest due to their ability to increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits. A particularly difficult part of these systems is the detector, where the optimal maximum-likelihood solution is desirable, but cannot be directly implemented due to its exponential complexity. This paper addresses this challenge and presents a digital circuit design for an 8×8 MIMO detection problem. A key feature is the integrated channel preprocessing unit, which performs the channel decomposition functions that are either omitted or performed "off-line" in other designs. The proposed device achieves near maximum likelihood bit error rate results at 57.6 Mbps. Other novelties include a high speed sorting mechanism and power saving features.
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