A Visual Dataflow Programming Environment for a Real Time Parallel Vision Machine

Abstract

Programming parallel architectures dedicated to real-time image processing (IP) is often a difficult and error-prone task. This mainly results from the fact that IP algorithms typically involve several distinct processing levels and data representations, and that various execution models as well as complex hardware are needed for handling these processing layers under real-time constraints. Our goal is to permit an intuitive but still efficient handling of such an architecture by providing a continuous and readable path from the functional specification of an algorithm to its corresponding hardware implementation. For this, we developed a data-flow programming model which can act simultaneously as a functional representation of algorithms and as a structural description of their corresponding implementations on a target computer built up of 3-D interconnected data-driven processing elements (DDPs). Algorithms are decomposed into functional primitives viewed as top-level nodes of a data-flow graph (DFG). Each node is given a known physical implementation on the target architecture, either as a single DDP or as an encapsulated sub graph of DDPs, making the well known mapping problem a topological one. The target computer was built at ETCA and embeds 1024 custom data-driven processors and 12 transputers in a 3-D interconnected network. Concurrently with the machine, a complete programming environment has been developed. Relying upon a functional compiler, a large library of IP primitives and automatic place-and-route facilities, it also includes various X-Window based tools aiming at visual and efficient access to all intermediary program representations. In terms of visual languages, we try to share the burden between all the layers of this programming environment. Rather than including some display facilities in existing software environment, we have taken advantage of the intuitiveness of functional representations, even textual, and of the hardware efficiency that provides immediate results, ultimately supporting hierarchical constructs.