A very large scale integrated circuits design laboratory for undergraduates

Abstract

The very large scale integrated circuit design course at Seattle University is discussed, with reference to the different kinds of software used since the course's inception in 1987. The first time the course was taught students used schematic capture to design and simulate their project. This is a laborious and time consuming method of design, but the students were enthusiastic about the possibility of designing large circuits. The next time the course was taught the students had access to a program called "Finesse" which is part of the Chipcrafter program. This program allowed the students to input their designs as a truth table. This was very much faster and simpler than schematic design and the students were very happy with the reduced design time. The "Finesse" systm of design was followed by the adoption of the Verilog hardware description language. Verilog seems to be very easy for the students to learn and use.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>