A Very High Linearity Twin Phase Interpolator With a Low-Noise and Wideband Delta Quadrature DLL for High-Speed Data Link Clocking

Abstract

A twin phase-interpolator (PI) architecture cancels most of the deterministic phase nonlinearity and achieves very high linearity across a wide frequency range with only four-phase input clocks. A delta quadrature delay-locked loop (Delta QDLL) is further proposed that generates wideband, low-jitter, and accurate quadrature clocks from the delay difference of two paths with a background analog quadrature tuning loop. A 1.2-V 65-nm CMOS prototype has a Delta QDLL with a quadrature accuracy of 0.9° from 3.5 to 11 GHz across ten chip samples. It consumes 7.8 mW at 7 GHz and has a 48.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {fs}_{\mathbf {rms}}$ </tex-math></inline-formula> jitter, yielding an outstanding figure of merit of −257.4 dB. The 7-bit twin PI achieves a less-than-1.45-LSB peak-to-peak integral nonlinearity ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {INL}_{\mathbf {pp}}$ </tex-math></inline-formula> ) from 3.5 to 11 GHz and the lowest <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {INL}_{\mathbf {pp}}$ </tex-math></inline-formula> of 0.72 LSB at 7 GHz. The PI has a 58.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {fs}_{\mathbf {rms}}$ </tex-math></inline-formula> jitter for a fixed PI control code. At 7 GHz with −1429-ppm clock modulation, the integrated fractional spur is as low as −41.7 dBc.