A Vertical Wafer Level Packaging using Through Hole Filled Via Interconnects by Lift Off Polymer Method for MEMS and 3D Stacking Applications

Abstract

A vertical wafer level packaging for MEMS has been developed with through hole filled via interconnects. Through hole filled via interconnects are formed on a cap wafer by electroplating method and bonded to the MEMS using wafer to wafer bonding method. A bottom up approach electroplating method is used for filling the through hole via interconnect. In the bottom up approach, a handler wafer is used for seed layer formation and the same time for the filling the via. Through hole vias are formed on a cap wafer by DRIE (Deep Reactive Ion Etching) method and the insulation and barrier layers are formed to isolate the silicon wafer. A lift off polymer is coated on a handler wafer and the seed layer is deposited on the polymer. The through hole via wafer and the handler wafer is bonded together using photo resist and is subjected to electroplating process. The handler wafer is separated from the through hole filled wafer by a combination of polymer lift off and ultrasonic agitation method. The completed through hole via filled wafer can be a device wafer or normal silicon wafer. This wafer can also be a cap wafer for MEMS wafer level packaging application and for 3D stacking applications