A versatile data cache for trace buffer support

Abstract

Since the cache system has been a predominant part of modern SoC's, we proposes a novel approach to enhance the versatility of the data cache by making it, called D/T (data/trace) cache, to function both as a regular data cache and as a trace buffer for real time processor monitoring and debugging. The cache structure is modified such that a portion of the cache ways can be configured as a trace buffer. The processor can then access the data cache and the trace buffer simultaneously. The trace can be dumped out with the existing cache write back circuitry. The experiments show that the D/T cache captures an average trace length of more than 2300 cycles in a 512 bytes of cache RAM with a very small hardware overhead of 892 gates and the miss rate of cache remains the same while using D/T cache. In addition, the D/T cache does not impact the critical path of the processor.