A variable round-robin arbiter for high speed buses and statistical multiplexers

Abstract

Resource arbitration is a fundamental problem in communication and computing system design. With the revolutionary improvements in optical and electronic interconnection technologies, a very fast arbiter design is required to match the speed of high performance buses or statistical multiplexers. This paper presents the design of a high speed VLSI arbiter that is capable of performing round-robin scheduling for N requests with P possible priority levels in O(( log log P)( log N)) time complexity and O( N log P) space complexity. The fairness of the arbiter is evaluated and possible enhancements to the arbiter are also discussed. To our knowledge, it is the first arbiter that can support variable priority arbitration with sublinear round-robin scheduling time complexity and linear space complexity. We have also shown that a high performance open system interconnection network can be built by the repetitive use of the proposed arbiter.