A Variability-Aware Robust Design Methodology for Integrated Circuits by Geometric Programming

Abstract

Process variations have continuously posed significant challenges to the performance and yield of integrated circuits (ICs). The performance modeling and robust optimization method considering process variations has become an important research task in today’s IC design. Aiming at solving the problems of strong nonlinearity and high-dimensional problems in circuit design, this paper proposes a general robust optimization method for ICs by geometric programming. This method first employs regularization sparse models to model a specific performance metric as a posynomial function in terms of design parameters, in order to reduce parameter space dimensionality and to accurately capture the nonlinear relationship between performance perturbations and process variations. Based on the posynomial performance models, this method further uses an uncertainty set to represent the uncertainties of process variations, and formulates the problem of robust optimization under process variations as a general geometric programming model that can be efficiently solved. Experimental results demonstrate that, the proposed method not only enhances the accuracy and efficiency of circuit performance modeling, but also improves the performance yield significantly compared with traditional circuit design methods.