A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning

Abstract

This article presents a universal modular hybrid low-dropout regulator (MHLDO) to provide any desired combination of the power supply rejection ratio (PSRR) and power conversion efficiency (PCE) with in-compliance output ripple, load transient response, and operating range while minimizing losses and decoupling capacitor. The hybrid architecture eliminates the need for the fine quantization of the digital LDO power gates and prevents any associated limit cycle oscillation while keeping the overheads low. It is configurable at design-time and robustly self-adjusts across different operating points via a scalable architecture. The modular topology overcomes significant challenges of developing a large variety of analog and digital LDOs in order to meet the varying PSRR and power budget requirements for systems on a chip (SoCs) in scaled CMOS. A nonlinear control (NLC) feature provides an energy-efficient way to respond to fast load transients, while the dynamic clamp strength tuning (DCST) technique prevents unnecessary oscillations stemming from the input parasitic inductances and improves stability while lowering switching losses. The designed MHLDO provides a programmable PSRR capability of up to -42 dB with a quiescent current of less than 27.3 μA as ALDO and a 133-mV worst droop against a >1-A/ns fast di/dt load change as DLDO. A new figure of merit (FoM) with improved accuracy demonstrates performance of 83 fs.