Abstract
Negative bias temperature instability (NBTI) strongly limits reliability of PMOS devices by degradation of threshold voltage, subthreshold slope and transconductance. The physical understanding of the NBTI mechanism is essential for searching paths of NBTI alleviation and providing realistic predictions for CMOS reliability. This work presents a new NBTI model based on hole trapping/detrapping accompanied by structural relaxation in the host dielectric. Simulations account for a time and T dependence of the drain current degradation during NBTI stress. Dynamic NBTI effects are then explained by alternative hole capture and emission during stress and relaxation stages. The impact of the activation energy dispersion on relaxation times is finally discussed.
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