A Unified Degradation Model of a-InGaZnO TFTs Under Negative Gate Bias With or Without an Illumination

Shuai Li,Qi Shan,Dongli Zhang,Mingxiang Wang,Huaisheng Wang

doi:10.1109/jeds.2019.2946383

Shuai Li, Qi Shan + Show 3 more

Open Access

https://doi.org/10.1109/jeds.2019.2946383

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Abstract

Degradation behaviors of amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors (TFTs) under negative bias stress (NBS) and negative bias illumination stress (NBIS) are investigated systematically. In some cases, a two-stage degradation behavior of a-IGZO TFTs is observed under both NBS and NBIS, which begins with a small positive shift of threshold voltage ( ${V} _{\mathrm{ th}}$ ), and is followed by a large negative ${V} _{\mathrm{ th}}$ shift. There is an intrinsic correlation between the degradations of NBS and NBIS. Quantitatively, both stress gate biases ( ${V} _{\mathrm{ G}}$ ) and temperature dependencies of $\Delta V_{\mathrm{ th}}$ of the two degradations are found to be the same and the recovery processes are also very similar. A unified model of NBS and NBIS is proposed to consistently explain the degradation behaviors of a-IGZO TFTs and their correlation.

Highlights

Amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors (TFTs) have attracted much interest for advanced displays such as active matrix organic light emitting diode (AMOLED) displays, due to their higher mobility and steeper subthreshold swing compared to a-Si TFTs [1], [2]
The negative shift of the TFT threshold voltage (Vth) under negative bias illumination stress (NBIS) has been attributed to holes trapping [4], where photo-excited holes injected into the gate insulator (GI) cause the negative Vth shift, or generation of where photo-excited V
negative bias stress (NBS) For the positive Vth shift of NBS degradation in a-IGZO TFTs, previous study attributed it to charge trapping into the gate insulator (GI) or at the channel/GI interface [10], [11]

Summary

INTRODUCTION

Amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors (TFTs) have attracted much interest for advanced displays such as active matrix organic light emitting diode (AMOLED) displays, due to their higher mobility and steeper subthreshold swing compared to a-Si TFTs [1], [2]. The negative shift of the TFT threshold voltage (Vth) under NBIS has been attributed to holes trapping [4], where photo-excited holes injected into the gate insulator (GI) cause the negative Vth shift, or generation of where photo-excited V ionized. There is no attention paid to relationship between negative bias stress (NBS) and NBIS degradation in literatures. Besides the normally observed continuous negative Vth shift of TFTs, a two-stage degradation behavior, which begins with an initial positive Vth shift first before the normal degradation, is observed in some. GI interface respectively for the positive and negative Vth shift. On this basis, the NBS and NBIS degradation of a-IGZO TFTs can be understood with the same mechanisms for the first time.

EXPERIMENTAL

RESULTS AND DISCUSSIONS

NBS DEGRADATION

TCAD SIMULATION

CONCLUSION