Abstract
A two-stage large-capacitive-load amplifier with multiple cross-coupled small-gain stages is proposed in this paper. The cross-coupled structure of the small-gain stages augments the large-signal responses, providing significant improvement in the effective output-stage transconductance and, hence, the gain–bandwidth product (GBW). Implemented in a standard 0.13- $\mu \text{m}$ CMOS technology and powered by a 0.7 V supply with a current consumption of $20~\mu \text{A}$ , the proposed amplifier achieves the GBW of 1.17 MHz and the phase margin of 74.8° while driving a capacitive load of 9.5 nF. The average slew rate is 0.3679 V/ $\mu \text{s}$ . The on-chip compensation capacitor is only 1.62 pF. The active chip area is 0.0056 mm2.
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