A Two-stage Area-efficient High Input Impedance CMOS Amplifier for Neural Signals

Abstract

In this article, a two-stage area-efficient high input impedance neural amplifier is proposed. It has been shown that two single-stage amplifiers with low gain will consume less area in comparison with a single-stage high gain amplifier for capacitively coupled amplifiers. Besides, splitting a high gain amplifier into two single-stages in this structure leads to achieving a higher input impedance at the end. Furthermore, it helps to boost the input impedance at a higher frequency. The robustness of the proposed structure is investigated by process and mismatch Monte Carlo simulations. All the simulations are run using in a commercially available 0.18 μm CMOS technology. Based on post-layout simulation, the proposed two-stage amplifier has 53 dB mid-band gain in the bandwidth of 5 Hz to 10 kHz. The input impedance is 2.8 GΩ and 56 MΩ at 1 kHz and 10 kHz, respectively. In comparison to a single-stage amplifier, the proposed structure boosted the input impedance at frequencies up to 1 kHz by a factor of 10 while the power consumption increased only 0.5 μW. Furthermore, the proposed two-stage neural amplifier area consumption is 0.02 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> without pads which decreased area consumption by a factor of 3.