A two-loop third-order multistage ΔΣ frequency to digital converter

Abstract

This paper presents a /spl Delta//spl Sigma/ frequency to digital converter based on two /spl Delta//spl Sigma/ phase-locked loops (PLLs). A primary /spl Delta//spl Sigma/ PLL performs frequency discrimination with first order noise shaping while a secondary /spl Delta//spl Sigma/ PLL performs a second order noise shaped measurement of the quantization phase error introduced by the primary PLL. Then, as in multistage A/D converters, the two digital outputs are combined to produce a cancellation of the quantization error introduced by the primary PLL . This paper presents results from a hardware prototype following the above concept, built with discrete ECL components. Measured results indicate that the circuit could function as a highly linear FM demodulator from an IF frequency or alternatively could form part of a frequency synthesizer. The secondary /spl Delta//spl Sigma/ PLL which provides a noise shaped phase error to digital conversion appears to be new. Its application to frequency synthesis is also discussed.