A Two-Dimensional Model for the Field-Plate Design of High-Voltage Transistor

Abstract

The field plate (FP) is a widely adopted concept and has been commonly used for high-voltage (HV) transistors to increase the breakdown voltage without enlarging the device dimension. In this article, a 2-D mathematical equation is derived for the FP design of HV transistors which reveals the potential and the electric field distributions in the reduced-surface field (RESURF) region. From the derived mathematical model, the mechanism of the FP-induced electric field suppression for the HV transistors is completely explained as the FP can reduce the potential gradient ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E} = -\nabla \varphi $ </tex-math></inline-formula> ) caused by the dielectric thickness differences above the RESURF region. The potential and the electric field distributions of the RESURF region will change as the FP is inserted due to the dielectric thickness variations. The derived equations also explained the capacitive behaviors and quantitatively described the potential and electric field distributions in different configurations of the FP-assisted RESURF devices. The results obtained by the derived equation are found to be very much accurate compared with technology computer-aided design (TCAD) simulation results.