A two-dimensional analysis of output overshoot mechanism in DAC current switch

Abstract

A detailed current switch output overshoot mechanism for a digital-to-analog converter (DAC) is analyzed, using a gate-level two-dimensional device simulator with input risetime and device topology as parameters. The importance of the carrier behavior around the emitter sidewall is stressed. The following conclusions are reached: (1) Output overshoot for a turn-on transistor rises in two steps. First the turn-on base-emitter voltage increases faster than input change and exceeds the final state value; then the emitter sidewall and corner regions become overcharged. Excess stored holes are discharged to the base center, which affects the settling time. (2) When the input risetime is too fast, the sidewall and the corner are further overcharged. When it is too slow, a fat region also becomes overcharged. In both cases, the settling time becomes long. (3) In the scaled transistor case, the settling time becomes shorter even if the input risetime is short and emitter-base voltage becomes higher, because the lateral potential transition delay in the flat region is shortened. >