Abstract
In this paper, a 120 frames per second (fps) low noise CMOS Image Sensor (CIS) based on a Two-Step Single Slope ADC (TS SS ADC) and column self-calibration technique is proposed. The TS SS ADC is suitable for high speed video systems because its conversion speed is much faster (by more than 10 times) than that of the Single Slope ADC (SS ADC). However, there exist some mismatching errors between the coarse block and the fine block due to the 2-step operation of the TS SS ADC. In general, this makes it difficult to implement the TS SS ADC beyond a 10-bit resolution. In order to improve such errors, a new 4-input comparator is discussed and a high resolution TS SS ADC is proposed. Further, a feedback circuit that enables column self-calibration to reduce the Fixed Pattern Noise (FPN) is also described. The proposed chip has been fabricated with 0.13 μm Samsung CIS technology and the chip satisfies the VGA resolution. The pixel is based on the 4-TR Active Pixel Sensor (APS). The high frame rate of 120 fps is achieved at the VGA resolution. The measured FPN is 0.38 LSB, and measured dynamic range is about 64.6 dB.
Highlights
The CMOS Image Sensor (CIS) is widely used in digital cameras, digital camcorders, CCTVs, medical equipment, etc
It shows very poor image quality due to the presence of high levels of random noise and of the column fixed pattern noise (CFPN) caused by the degraded Analog to Digital Converter (ADC) linearity error from the analog gain difference between the two ramps
This paper described a CMOS image sensor with a Two-Step Single-Slope ADC, a high speed frame rate of 120 fps, a low fixed pattern noise (FPN), and a column self-calibration technique
Summary
The CMOS Image Sensor (CIS) is widely used in digital cameras, digital camcorders, CCTVs, medical equipment, etc. The frame rates are determined by the conversion speed of the Analog to Digital Converter (ADC) that exists in every column These days, most CIS systems in a variety of applications use a Single-Slope ADC (SS ADC) because of a simple structure and excellent linearity [1]. Such a system has a disadvantage in that the conversion speed of the SS ADC slows down at a rate of 2n times in proportion to an increase in the resolution (n). Cyclic ADC or Successive Approximation Register (SAR) ADC are well-known techniques for the high frame rate
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