A Trigger Demonstrator for the L0 Muon Barrel Trigger of the ATLAS Experiment for HL-LHC

Abstract

The ATLAS Collaboration has planned significant upgrades to the muon system, in order to cope with the instantaneous luminosity that will be delivered by the Large Hadron Collider machine. The upgrades will allow the Muon Spectrometer to keep and improve its current performance for the High Luminosity LHC program expected to start in 2027. Together with the detector, most of the trigger and readout electronics of the Muon Spectrometer will be replaced, so that all hit data will be optically transferred from the frontend to the backend boards, where the first-level muon trigger will be executed with latency of 10 μs and maximum trigger rate of 1 MHz. For the Barrel region, the first-level muon trigger algorithm is performed off-detector by 32 ATCA FPGA-based boards, called Sector Logic, which receive detector data, perform the first-level algorithm, use the muon candidate track information from the Monitored Drift Tubes detectors and send the muon trigger candidate information to the Central Trigger Processor. In this work, we present a proof of concept of the trigger candidate identification algorithm for the first-level muon trigger in the barrel region. It is executed in the Sector Logic FPGA and it is based on a massive use of Digital Signal Processors Slices available in a Xilinx FPGA device. The algorithm is able to identify up to three muon candidates with a transverse momentum higher than a given threshold, and uses the Digital Signal Processors features of manipulating a large amount of bits and of providing results of its calculation in few clock cycles, with a low and deterministic latency. We discuss a first implementation of our architecture in a Xilinx Evaluation board based on a Kintex-7 FPGA, although the design can be easily targeted to newer or larger devices, such as the Ultrascale+ that will be used in the experiment. We describe the logic resources occupation of the design, its performances in terms of maximum operation frequency and latency.