Abstract
This paper introduces a 401–457 MHz BFSK transmitter (TX) architecture that utilizes mixing and image rejection techniques to generate the two carrier frequencies for BFSK transmission. The proposed architecture enables low power consumption for a wide range of data rates by avoiding fast settling time requirements for the frequency-locked loop. Simulations indicate that the TX designed in 130nm CMOS technology can achieve data rates up to 10 Mbps with a power consumption of 140 μW or lower from a 0.6 V supply. Its estimated energy efficiency is 14 pJ/b while delivering −19.7 dBm of output power.
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