A Transistor-Level Probabilistic Approach for Reliability Analysis of Arithmetic Circuits With Applications to Emerging Technologies

Abstract

Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (mosfet) for computing applications. The focus of this paper is on the analysis of reliability of combinational logic circuits at the transistor level with the goal of application to these technologies. To this end, we present an approach for the calculation of the output probabilities for basic logic primitives that comprise a combinational circuit. Using the output probabilities, a computationally efficient algorithm (based on Hadamard product) is presented to calculate the reliability. As an application of the proposed algorithm, we analyze the reliability of adder circuits composed of carbon nanotube FETs considering fabrication-level parameters. We then investigate adder characteristics that lead to high reliability independent of the technology. In particular, we propose a new multibit adder termed hybrid adder offering high reliability with low area requirement for various transistor-based emerging technologies. Detailed simulation results are presented to support the analysis.