Abstract
In this paper, a fast transient noise simulation model is proposed to analyze the optimal number of stages for the maximum signal to noise ratio (SNR) of the analog accumulator in a fixed silicon area. The Transient Noise Simulation (TNS) is required to confirm the analysis of the optimal number of stages, which requires long simulation time. In order to accelerate our analysis, a fast transient noise simulation model (TNSM) is proposed based on the noise analysis and shown to be effective by TNS. Numerical analysis is verified by the TNSM, and it indicates that the optimal number of stages in a fixed area changes with the noise of the input signal.
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