A Trace Based Framework for Validation of SoC Designs with GALS Systems

Abstract

Composing synchronous intellectual property (IP) blocks over asynchronous communication links for an system-on-chip (SoC) design is a challenging task, especially for ensuring the functional correctness of the overall design. In this paper, we propose a trace based framework to assist in validation of globally asynchronous locally synchronous (GALS) designs. We provide a specific characterization of synchronous IPs in our framework such that a simple barrier synchronization protocol would be sufficient for asynchronous communication between them. We theoretically show that IPs with single activation property, composed asynchronously, are behaviorally equivalent to those composed synchronously.