A Topology Optimization Method of Application-Specific Network-on-Chip

Abstract

Future high-end System-on-chips (SoCs) will be consisted of hundreds of cores integrated on a single chip. On-chip communication becomes the major performance bottleneck of SoCs. Network-on-Chip (NoCs) have become as the most prominent solution to on-chip communication problems. Network topology which affects the total network conformance is basic of network related researches. The objective of topology synthesis is to minimize the power consumption and router resources while satisfying bandwidth constraints. In this paper, we present a two-level genetic-algorithm (GA) based technique to synthesize application-specific NoC topology. Comparing to an existing three-level GA, experiments show that our technique saves 1.8% energy while saving great runtimes of 97.79%. Our technique generates approximate optimal topology less than one minute.