A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow

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Design methodologies for synthesizing FPGA fabrics presented in the literature typically employ a bottom-up approach wherein individual tiles are synthesized in isolation and later stitched together to generate the large FPGA fabric. However, using a bottom-up methodology to ensure fabric-level performance targets is challenging due to the lack of a global timing view across multiple tiles spanning the FPGA fabric. While previous works address this problem with a combination of manual buffering and floorplanning, these additional steps introduce significant deviations from standard push-button ASIC flows. In this paper, a top-down synthesis methodology is proposed, which eliminates the need for floorplanning and manual buffering by providing a global timing view of the FPGA fabric. To evaluate the proposed design methodology, we developed an FPGA fabric generator using the Chisel hardware construction language. The fabric generator reads in the Verilog-to-Routing architecture file, describing the user-defined FPGA fabric, and generates the Verilog netlist and timing exceptions required to automatically place and route the FPGA fabric in any technology node with a standard cell library. Post layout timing analysis of placed and routed FPGA fabrics on a 28nm industrial CMOS process demonstrates that the top-down methodology can place and route fabrics without the need for any manual buffering or floorplanning while providing ~20% average improvement in performance across multiple benchmark designs.