Abstract
We present a tool for synthesis of pipelined implementations of hardware-software systems. The tool uses iterative hardware-software partitioning and pipelined scheduling to obtain optimal partitions which satisfy the timing and area constraints. The partitioner uses a branch and bound approach with a unique objective function which minimizes the initiation interval of the final design. It takes communication time and hardware sharing into account. This paper also presents techniques for generation of good initial solution and search space bounding for the partitioning algorithm. A candidate partition is evaluated by generating its pipelined schedule. The scheduler uses a list based scheduler and a retiming transformation to optimize the initiation interval, number of pipeline stages and memory requirements of a particular design alternative. The effectiveness of the tool is demonstrated by experimentation.
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