A timing analyzer for multiple clock phase designs with level‐sensitive latch feedback loops

Abstract

AbstractThis paper proposes a method for the high‐speed timing analysis of the multiple clock phase synchronized circuit. In general, the static timing analysis can be executed by the computational complexity which is independent of the input pattern.In the traditional method of handling the multiple clock phase synchronized circuit, however, the timing analysis of the circuit requires the number of periods, which depends on the circuit structure, such as the number of latch stages in the longest path in the circuit. In addition, independently of whether or not there exists a loop containing a latch, the same number of elements as that of the clock phases must be examined in a period.A larger number of processings is always required when there exists a loop. By contrast, in the proposed method, each element is examining exactly once, if there does not exist a loop. Even if there exists a loop, the processing can be executed by the number which is independent of the number of phases. The number is several in the typical practical circuit. Thus, the speed is improved by the proposed method by restricting the timing analysis over multiple phases and multiple periods into a single period (the proposed timing analysis in a period, in the sense of this paper, is of a multiplexed nature since the verification extends over multiple phases and multiple periods).