Abstract

The paper presents a vernier delay line (VDL) type of time to digital converter (TDC) using time amplification technique. The proposed time amplifier (TA) architecture is aim to provide larger input range and higher gain. Simulation results indicated that the maximum deviation between ideal and actual TA transfer curve has been reduced to about 30ps, and the input range and gain are 160ps and 16 respectively. The TDC has maximum sampling rate of about 50Msps when using 200MHz reference clock and the time resolution of 39ps with the differential non-linearity (DNL) within −0.6 and 1 LSB, and the integral non-linearity (INL) within −1.4 and 1 LSB. The TDC is realized using the CMOS 0.18um 1P6M technology.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.