A Time-Interleaved Ring-VCO with Reduced 1/ $\text {f}^{3}$ Phase Noise Corner, Extended Tuning Range and Inherent Divided Output

Abstract

This paper describes a time-interleaved (TI) ring-VCO (RVCO) exhibiting an improved phase noise over a wide range of frequency offsets, an extended tuning range and an inherent divided output. Such features are achieved by substantially increasing the number of delay stages in a RVCO, such that the rich multi-phase sub-outputs can be combined through a time-interleaved method, generating a high-frequency output with a significantly lowered 1/ $\text {f}^{3}$ phase noise corner ( $\mathrm {f}_{\mathrm {1} / \mathrm {f}^{3}}$ ). The critical block is the phase combiner, which features a timing window to minimize the delay offset and mismatch. A reconfigurable TI factor extends the tuning range over the same range of supply voltage ( $\text {V}_{\mathrm {DD}}$ ). The prototype is a 35-stage dual-mode TI-RVCO occupying 0.003 mm2 in 65 nm CMOS, and has a selectable TI factor of 5 and 7. The measured $\mathrm {f}_{\mathrm {1} / \mathrm {f}^{3}}$ is 150 kHz at 3.47 GHz, which is $6.2\times $ less than that of a typical 5-stage RVCO. The tuning range covers 1.7 to 3.5 GHz (68.5%) over $\text {V}_{\mathrm {DD}} = 0.7$ to 1 V. The multi-phase sub-outputs are the inherent divided output ( $\div ~5$ or $\div ~7$ ) that can be directly utilized in a PLL to save area and power.