A time-interleaved chopper-stabilized delta-sigma analog to digital converter

Abstract

Although /spl Delta//spl Sigma/ modulators are widely used for low to moderate rate analog-to-digital conversion, the time oversampling requirement has limited their application to higher rate converters. This paper presents a new architecture of time-interleaved /spl Delta//spl Sigma/ ADC using chopper-stabilized techniques in order to eliminate the low frequency noise. The new architecture has identical performances to the regular time-interleaved /spl Delta//spl Sigma/ ADC but is immune to low frequency noise and DC offsets. Such an architecture can be obtained without adding hardware complexities. In consequence, the architecture offers the potential of integrating high-precision, high-speed ADCs together with digital signal processing functions using VLSI processes optimized for digital circuitry. The paper presents the general architecture and provides a performance analysis closely supported by computer simulations.