Abstract
In this paper a simple time-domain line model for power dissipation calculation for CMOS buffers driving lossy transmission line is presented. The main benefits of the proposed model is its simplicity, maintaining the merit of a lumped-circuit model, that leads to great simulation efficiency. It requires in fact, a single resistor to calculate with sufficient accuracy both power dissipation aliquots in the CMOS-line-driver and in intra-chip lossy interconnects for modern VLSI integrated circuits.
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