A Time-Interleaved Multimode RF-DAC for Direct Digital-to-RF Synthesis

Abstract

A multimode delta-sigma ( $\Delta\Sigma$ ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. The proposed circuit uses a single clock frequency ( $f_{s}$ ) and provides a $\Delta\Sigma$ modulator (DSM) that operates in bandpass (BP) and highpass (HP) modes to synthesize signals around $f_{s}/4$ , $f_{s}/2$ , or $3f_{s}/4$ . The on-chip 14 bit second-order DSM implements an array of 1 bit pipelined subtract functions to generate 3 bit $f_{s}$ rate RF-DAC input data. Analog interleaving via a second 3 bit DAC is used to reject the first DAC image, simultaneously doubling the usable bandwidth of the HP DSM and increasing the SNR. Calibration circuits are added to the DAC to compensate for amplitude and timing variations. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS with an area of $0.563 \text{mm}^{2}$ . Measurements at $f_{s}= 2 \text{GHz}$ yield an output power of $-0.6 \text{dBm}$ with 76.2 dB signal-to-image-rejection ratio (SIRR), 76.2 dB SFDR over a 100 MHz bandwidth, $-80 \text{dBc}$ IM3, $-67.2\;\text{dB}$ WCDMA ACLR, and $-\text{66.4} \text{dBc}$ LTE ACLR. Changing $f_{s}$ to 3 GHz allows frequencies of 2.25 GHz to be generated with output power of $-16.6 \text{dBm}$ , 65.2 dB SFDR, $-62 \text{dBc IM}3$ , $-59.3 \text{dB}$ WCDMA ACLR, and $-59.2 \text{dBc}$ LTE ACLR.