Abstract
Recently there has been a great deal of interest in load-balancing switches due to their simple architecture and high bandwidth. In this paper we propose a three-stage load- balancing switch along with output load-balancing to address the mis-sequencing problem. We show that our proposed scheme provides a delay guarantee bounded by the delay of an OQ switch with the same input traffic plus a constant while achieving 100% throughput for admissible traffic with (sigma, rho) -upper constraint.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
