A three-stage CMOS operational amplifier with high gain and phase margin

Abstract

A novel three-stage CMOS operational amplifier (Op-amp) with high phase margin and high GBW is presented in this paper. The proposed Op-amp has the capability of driving large capacitive loads. Design of frequency compensation network for multistage CMOS Op-amp is always a big concern for researchers as design of compensation network is not quite simple and occupies large space on chip. Compensation network exploited exclusively for this Op-amp has an amalgamation of a very small valued single miller capacitor and differential amplifier and the network has been put in feed forward path. Use of smaller miller capacitor is preferred for low die area on chip and circuit complexity. All transistors of the proposed amplifier are biased by using supply voltage only without using any external current source. The simulated three stage Op-amp exhibits an open loop gain, the unity-gain bandwidth and phase margin as 122 dB, 2.77 MHz and 82.61° respectively. All simulations are done using 0.18 um technology with a 1.8V power supply.