A three-terminal band-trap-band tunneling model for drain engineering and substrate bias effect on GIDL in MOSFET

Abstract

A new three-terminal partial band-trap-band tunneling (BTB) model is proposed to predict the drain engineering effect and substrate bias effect on gate-induced-drain-leakage (GIDL) characteristics for virgin devices free from electric stress. The lateral field /spl epsiv//sub L/ and the ratio of lateral field w.r.t. total field /spl epsiv/(/spl epsiv//sub L///spl epsiv/) are two key factors responsible for the tunneling barrier lowering and the enhancement of GIDL. The principle to suppress GIDL are two-fold: the first one is to eliminate process induced intrinsic interface states and the second one is to minimize /spl epsiv//sub L/ and /spl epsiv//sub L///spl epsiv/ by using drain engineering or changing bias conditions such as applying forward substrate biases.