Abstract
This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc.
Highlights
The demand for higher data rate in modern communication and computing systems has resulted in a sharp increase in the operating frequencies of digital circuits and systems
First example presents jitter at the output of a tapered buffer used in the clock distribution network
Second example presents power supply induced jitter (PSIJ) at the output of a delay-line including the effect of on-chip interconnects
Summary
The demand for higher data rate in modern communication and computing systems has resulted in a sharp increase in the operating frequencies of digital circuits and systems. The design of integrated circuits is becoming more challenging due to the rigid timing and layout constraints as well as narrow timing margins These challenges are further aggravated by the power supply noise (PSN) which is becoming one of the major performance limiting factors in high-speed low-power digital systems due to its impact on both amplitude and timing of the signal. A generalized methodology is presented for estimation of power supply induced jitter (PSIJ) in a chainof-inverters with the following contributions: 1) The proposed approach is generic and can be used for both cases, an inverter chain with same sizing of inverters as well as tapered buffers.
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