A testable design for asynchronous fine-grain pipeline circuits

Abstract

Asynchronous fine-grain pipeline circuits with dynamic gates are increasingly being used for high-performance datapath design in both synchronous and asynchronous processors. The dynamic gates intrinsically have storage elements for their outputs, which can implicitly function as pipeline latches. Therefore, most of fine-grain pipeline circuits are realized without explicit through-latches. For a testable design of such circuits, it is not reasonable to design a scan path with normal scan latch libraries from the viewpoint of area and performance penalty. We present a new testable design, for such asynchronous fine-grain pipelines with little penalty of performance and area overhead. The SPICE simulation shows that the performance overhead for the proposed design is 3.7% with a 0.4 um CMOS technology.