A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns

Abstract

Recently, it is very important to reduce the number of test patterns by using design-for-testability (DFT) with the increase in test costs for VLSI. Especially DFT methods to reduce the number of test patterns at register transfer level (RTL) are required for the adaptability of traditional VLSI design flows and the reduction of time to search DFT locations. In this paper, we propose a DFT method at RTL to enable hardware elements including operational units and multiplexers to be concurrently tested with as small number of test patterns as possible in scan testing. The proposed method enhances the effectiveness of test compaction by assigning test registers for hardware elements such that efficient concurrent testing is executed based on controller augmentation. Experimental results on high-level benchmark circuits show that our proposed method reduced the number oftest patterns by 33%with 7.1 % area overhead on average compared with full scan design.