Abstract
This paper addresses the problem of generating test patterns for sequential circuits, and presents a method using some efficient data structures aimed at minimising simulation and test generation time, while working with the constraint of limited memory. We have implemented the suggested algorithms on an IBM PC/AT compatible and have been able to obtain complete fault coverage by introducing a minimal set of test pins in addition to the primary outputs as observable test points. This eliminates the hardware overhead incurred when using scan based designs to incorporate testability.
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