A Temperature Compensated Triple-Path PLL With $K_{\mathrm {VCO}}$ Non-Linearity Desensitization Capable of Operating at 77 K

Abstract

A novel triple-path PLL (TPPLL) is presented to compensate the VCO frequency drift caused by the large temperature variations meanwhile maintaining a stable bandwidth and good jitter performance. The proposed PLL architecture splits the VCO tuning loop into three paths as the proportional, the integral, and the temperature compensation (TC) path, respectively. The feed-forward TC path with a large VCO gain but a small bandwidth is adopted to realize the compensation for the VCO frequency temperature drift in a closed-loop manner without affecting the high-frequency performance of the VCO. The fixed control voltage on the proportional path and limited control-voltage variation on the integral path desensitize the VCO gain (K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VCO</sub> ) non-linearity and stabilizes the loop bandwidth over large temperature range. The small VCO gain on the proportional and integral paths contributes to low phase noise and spurs. In addition, the different gain settings for the separate proportional and integral paths work as a capacitor multiplier, leading to saving on the silicon area of the loop filter. A prototype TPPLL at 2.56 GHz using a 65-nm CMOS process has been implemented and measured. The core circuits occupy an area of 0.08 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and consume 8.5 mW. The silicon measurement results show that this PLL can continuously work (without calibration) when the temperature changes from 300 K down to 77 K, and has a frequency drift reduction by 99%, while keeping good jitter performance across the entire temperature range.