A Temperature Compensated Read Assist for Low Vmin and High Performance High Density 6T SRAM in FinFET Technology

Abstract

A low Vmin, 6T-SRAM is realized in 7nm FinFET Technology using read and write assist methods. Read margin of the SRAM cell is recovered using a temperature compensated wordline lowering scheme. This temperature compensated Read Assist provides additional advantage that lowering on wordline is almost process independent that makes Read Assist very robust. This scheme makes design free from tuning after post silicon. Since Proposed Read Assist circuit lowers Wordline at high temperature while lowering at low temperature is very minimal, SRAM writability is not impacted by Read Assist Circuity at low temperature. At low voltage, SRAM performance is limited by Read cycle time. The proposed Read Assist scheme improves Read performance by 200%, which in-turn reflects the gain in operating frequency up to 100%. In the proposed Read assist implementation operating frequency is almost comparable to system when Read Assist is not enabled with added advantage of low voltage enablement