Abstract
This paper presents an IP (intellectual property) block for configurable N-bit binary-to-binary logarithmic conversion based on Mitchell's algorithm. The IP block is verified with 0.18 mum CMOS technology for N is 16, 32, and 64 bits. In each implementation, the IP block calculates a logarithmic value in one clock cycle. Although the IP block is implemented in 0.18 mum CMOS technology, the IP block is technology independent and, therefore, can be easily be re-usable for different processing technologies.
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