A technology for building shallow junction MOSFETs on vertical pillar walls

Abstract

This work addresses a fundamental problem of vertical MOSFETs, that is, inherently deep junctions that exacerbate short channel effects (SCEs). Due to the unconventional asymmetric junctions depth in vertical MOSFETs, it is necessary to look separately at the influence of each junction especially the drain junction on the potential distribution in the channel and hence the SCEs. A self-aligned shallow junction is easily formed at the bottom of a conventional vertical pillar but in order to further suppress the SCEs we explore the formation of a shallow drain junction on the top. A self-aligned oxide region, or junction stop (JS) is formed at the top of the pillar and acts as a hard mask to allow the formation of a shallow drain. The efficacy of this approach to forming shallow junction MOSFETs on vertical pillar walls is demonstrated by simulation with the influence of JS on SCEs clearly shown. Finally, the electrical performance of experimental JS devices is described and discussed in the context of characterization and modeling