Abstract
Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors) or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high‐performance computing applications found in meteorology or high‐energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems.
Highlights
The usage of Multiprocessor System-on-Chip (MPSoC) for accelerating performance intensive applications is an upcoming trend in current chip technology
This paper describes the new taxonomy and validates it by classifying several existing static and dynamic singleand multiprocessor systems
The Data Flow Dependent Communication Infrastructure Processor (DFDCip) is a model for the communication infrastructure of the runtime adaptive multiprocessor system-on-chip (RAMPSoC) approach, which can be handled as a processor providing communication interfaces on-demand
Summary
The usage of Multiprocessor System-on-Chip (MPSoC) for accelerating performance intensive applications is an upcoming trend in current chip technology. The partitioning algorithms and methodologies are able to detect inherent parallelism in a dataflow graph (DFG), and a mapping tool is able to distribute the tasks to a certain processing unit The gap in this procedure is that the tasks can only be optimized to a certain extent to a given (multi)processor architecture. This paper describes the new taxonomy and validates it by classifying several existing static and dynamic singleand multiprocessor systems. It is validated by a runtime adaptive multiprocessor system-on-chip (RAMPSoC) [6].
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