A systolic architecture for high-performance scaled residue to binary conversion

Abstract

The scaled Chinese remainder theorem (CRT) is a very useful tool in residue arithmetic. Its properties can be exploited for the simplification and speeding-up of the conversion process. The main drawback presented by this methodology, when it is used for the output conversion, is the need of long wordlength look-up tables (LUTs) storing the correspondence among the modular numbers and the corresponding scaled terms of the CRT. This fact limits the maximum speed obtainable by this approach. In this brief, a new method for the computation of the scaled terms is presented. It has been implemented by using very small wordlength LUTs and simple arithmetic operators. The only proviso is that the moduli must be odd. The obtained architecture is very fast and due to the local interconnections is suitable for an efficient VLSI implementation.