A system-on-a-chip architecture for power signal processing

Abstract

The basic underlying signals of interest in power engineering applications, such as relaying protection, metering or synchronization, are fundamental components, sequence components or signals that indicate a change in the system state. This paper explores a system-on-a-chip architecture that can accommodate the needs of the power engineering community and can reduce the number of variable parameters and chip real estate. A novel dual filter scheme is presented to emulate the properties of a delay line. A variable sampling technique is used to adapt to input frequency variations. A multiinput multioutput finite input response filter cascaded with a median filter provides sequence component information in real time. All signal processing is done in synchronism with the line frequency. The synchronization circuit is insensitive to voltage sags or surges and harmonics. Simulation models prototyped in VHDL are investigated and used to verify the developed concepts. Finally, in-circuit tests are performed using an Altera FPGA chip.