Abstract

Advancements in technology have made deep learning a hot research area, and we see its applications in various fields. Its widespread use in silicon wafer defect recognition is replacing traditional machine learning and image processing methods of defect monitoring. This article presents a review of the deep learning methods employed for wafer map defect recognition. A systematic literature review (SLR) has been conducted to determine how the semiconductor industry is leveraged by deep learning research advancements for wafer defects recognition and analysis. Forty-four articles from well-known databases have been selected for this review. The articles’ detailed study identified the prominent deep learning algorithms and network architectures for wafer map defect classification, clustering, feature extraction, and data synthesis. The identified learning algorithms are grouped as supervised learning, unsupervised learning, and hybrid learning. The network architectures include different forms of Convolutional Neural Network (CNN), Generative Adversarial Network (GAN), and Auto-encoder (AE). Various issues of multi-class and multi-label defects have been addressed, solving data unavailability, class imbalance, instance labeling, and unknown defects. For future directions, it is recommended to invest more efforts in the accuracy of the data generation procedures and the defect pattern recognition frameworks for defect monitoring in real industrial environments.

Highlights

  • Silicon chips are the backbone of the current digital era

  • Manufacturing industries, semiconductor fabrication companies aim for maximum productivity by taking measures against yield limiting factors

  • IEEE Transactions on Semiconductor Manufacturing is on the top of the list with seventeen publications

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Summary

Introduction

Silicon chips are the backbone of the current digital era. The advancements in the emerging technologies of Internet of Things (IoT), Fifth Generation (5G) telecommunication networks, Artificial Intelligence (AI), and the automotive industry have propelled their consumption [1], [2]. Keeping up with the growing demand for semiconductor devices by embracing the efficient, most suitable manufacturing automation practices is more critical in present times. Manufacturing industries, semiconductor fabrication companies aim for maximum productivity by taking measures against yield limiting factors. Wafer fabrication defects are significant [3]. Controlling the ratio of defective Integrated Circuits (ICs) determines an IC foundry or wafer fabrication facility (fab)’s productivity and indicates its control on the manufacturing processes [4]. The defects caused by the frontend operations in circuit fabrication reflect the manufacturing equipment and processes’ flaws. They are characterized as random and systematic defects based on their originating factors [5].

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