Abstract

This work introduces a design procedure for two-stage class AB opamps which minimizes power consumption for a given specifications set. The proposed procedure has been applied to the redesign of published opamps for comparison target, demonstrating the procedure validity by improving their efficiency. The systematic procedure is then applied to an opamp that will be part of the readout of an imager. The opamp is designed in a 0.35 /spl mu/m 3.3V standard CMOS technology and exhibits GBW /spl equiv/49MHz, SR /spl equiv/ 74V//spl mu/s, 0.1% settling time of 43ns, consuming only 0.87mW with a die area of 0.0053mm/sup 2/.

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