A systematic approach to reduce non idealities in pentacene bottom-contact bottom-gate transistors

Abstract

We present a step by step guide to optimize the fabrication process and develop Pentacene transistors with greatly diminished non-idealities. The issues addressed in this work are (a) non-Ohmic metal-semiconductor interface (b) trap states at the insulator-semiconductor and metal-semiconductor interfaces and (c) gate leakage. These factors ((a)-(c)) limit the charge carrier transport and this is reflected as distortions in the electrical characteristics compared to that expected for an ideal case. We demonstrate a simple model to correct the gate leakage in the experimental data. An integrated shadow mask is employed to reduce the gate leakage in the transistors. Palladium as an injection layer with chromium as an adhesion layer is found to show the least contact limitation effect (i.e. elimination of S-type output characteristics). Thiols and organosilane are used to treat the insulator surface to reduce the current-voltage hysteresis and adjust the switch-on voltage. OctaDecylTrichloroSilane treatment is found to yield near zero switch-on voltage with negligible current-voltage hysteresis.